`timescale 1ns/1ps
module tb_gls;

  // 时钟与复位
  logic clk = 0, rst_n = 0;
  always #2.5 clk = ~clk;  // 200 MHz
  initial begin
    rst_n = 0; #20; rst_n = 1;
  end

  // DUT 实例化（门级网表）
  riscv_npu_soc dut (
    .clk(clk),
    .rst_n(rst_n),
    .tck(1'b0), .tms(1'b0), .tdi(1'b0), .tdo(),
    .apb_paddr(32'd0), .apb_psel(1'b0), .apb_penable(1'b0),
    .apb_pwrite(1'b0), .apb_pwdata(32'd0),
    .apb_prdata(), .apb_pready(), .apb_pslverr()
  );

  // 加载 SDF
  initial begin
    $sdf_annotate("gls/sdf/riscv_npu_soc_syn.sdf", dut);
    $display("SDF annotated successfully.");
  end

  // 复用 RTL 测试
  `include "verification/tests/npu_dotp_test.sv"
  npu_dotp_test gls_test;

  initial begin
    gls_test = new();
    gls_test.run_phase(null);
    $finish;
  end

  // 超时保护
  initial begin
    #100000 $display("ERROR: Simulation timeout!"); $finish;
  end

endmodule